1. Field of the Invention
The present invention relates to an Synchronous Transport Module Level 1 (STM-1) interface block, and in particular to a Channel Associated Signaling (CAS) data processing apparatus capable of effectively processing CAS signaling data.
2. Background of the Related Art
Generally, a base-to-base interface of an exchanger for processing voices is performed through a 2.048 Mbps T1/E1 link. However, because many cables are required to connect a plurality of the T1/E1 link to the opposite exchanger, a T1/E1 signal is typically multiplexed/demultiplexed into T3/STM-1 signal through transmission equipment. The multiplexed signal is then transmitted/received .
FIG. 1 is a block diagram illustrating a first related art connection construction between exchangers. Exchangers 10, 13 are separately connected to MUX/DEMUXs 11, 12 through 63 E1 links. The MUX/DEMUXs 11,12 are connected to each other through an STM-1 link. The 63 E1 signals outputted from the exchanger 10 are thus multiplexed into an STM-1 signal in the MUX/DEMUX 11 and then transmitted to the STM-1 link. The MUX/DEMUX 12 demultiplexes the transmitted STM-1 signal into the original 63 E1 signals and outputs them to the exchanger 13. Accordingly, E1 base communication between exchangers 10, 13 can be performed.
The exchangers 10, 13 each include 16 E1 interface cards (not shown). Each E1 interface card processes a signal with respect to 4 E1 links. When the E1 interface cards are operated in as a CAS (Channel Associated Signaling) mode, they provide a CAS signaling data (hereinafter referred to signaling data) processing for each channel (time slot), an alarm function for the links, and various test functions. CAS is the transmission of signaling information within the channel.
FIG. 2 is a block diagram illustrating the conventional E1 interface card of the exchangers 10, 13 of FIG. 1.
Framers 100-1˜100-4 receive a signaling data stream from 4 E1 links, respectively, and local memory (LM) 101 temporarily stores the signaling data outputted from the framers 100-1˜100-4 through a CPU 102. The CPU 102 performs general control operations of the E1 interface card. The CPU 102 also reads the signaling data stored in the LM 101 and reformats it into a report data. A common memory (CM) 103 stores the report data temporarily, and interfaces the E1 interface card with a upper processor 104.
In operation, the framers 100-1˜100-4 perform interface operations with respect to the 4 E1 links respectively, and read the signaling data stream from the corresponding link. The data stream is then stored in its register. Once the signaling data streams are stored, the CPU 102 outputs control signals to the framers 100-1˜100-4 and reads the signaling data streams from the register of the each framers 100-1˜100-4. Accordingly, as depicted in FIG. 3A, for one link, the signaling data steams about 32 channels (time slot) are read from the register, and are stored in the LM 101. The above operations for the other E1 links are repeated.
When the signaling data streams storing is completed, the CPU 102 reads the signaling data streams stored in the LM 101, reformats it into the report data depicted in FIG. 3B, and stores it on the CM 103. The above operation is performed in 8 msec real time cycle, and the processing for the signaling data stream of the 4 links has to be completed in 8 msec. Accordingly, the upper processor 104 performs the control operation for the STM-1 interface block by accessing the report data stored in the CM 103.
However, in the first related art connecting construction of the exchanger, because the E1 links have to be extended to a multiplexer 11 and demultiplexer 12, it causes expense increase and maintenance/repair difficulties. Accordingly, in order to solve above-mentioned problems and to process the E1 link more efficiently, a second connecting construction of the exchanger, as depicted in FIG. 4, is generally used.
As depicted in FIG. 4, in the second related art connection construction of the exchanger, the MUX/DEMUX included in transmission section of the first connecting construction are integrated with the exchangers 20, 21. That is, the exchanger 20, 21 include a STM-1 interface block 30 for a physical interface. The STM-1 block 30 includes a STM-1 link interface 30-1, a synchronous digital hierarchy (SDH) 30-2 and an E1 processing unit 30-3.
The STM-1 link interface 30-1 transmits and receives STM-1 signals and the SDH 30-2 constructs the STM-1 signal by multiplexing/demultiplexing the E1 signal in accordance with an ITU-T (International Telecommunication Union-Telecommunication) recommendation. The E1 processing unit 30-3 processes the E1 links in the same way as the first related art E1 interface card (FIG. 2). The E1 processing unit comprises 3 E1 interface cards, each of which processes 21 E1 links respectively.
Accordingly, the E1 processing unit 30-3 of the STM-1 interface block 30 performs various functions such as signaling signal processing, alarming, and error processing. Here, the operations, except for the test function, should be processed in real time by the E1 processing unit 30-3. The above functions thus have to be performed in an 8 msec cycle in accordance with a system (upper processor) request.
The conventional E1 interface card adapted to the first connecting construction of the exchanger has various problems. For example, it only performs the processing with respect to the 4 E1 links. Accordingly, if the number of E1 links to be processed is increased, the number of the E1 interface cards and CPUs also have to be increased. This results in complex circuit construction and other difficulties. For example, to process 63 E1 signals, 16 E1 interface cards and 16 CPUs for the 16 E1 interface cards are required.
In addition, the conventional E1 interface card can be used only when the number of E1 links is low. In other words, the load of the CPU needs to be small. Accordingly, if 21 E1 links are present for processing in the STM-1 interface block of the second connecting construction, the related art E1 interface card cannot be used as it is. In other words, when the number E1 links increases, the signaling data processing time is increased in proportion to the number of links. Consequently, the related E1 interface card having the limited CPU processing speed cannot process the signaling data in the required 8 msec.
Also, to solve above-mentioned problem, the high speed CPU may be used, but it is not economical due to its expensive price.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.